The present invention relates to a semiconductor integrated device (hereafter referred to as an LSI) and more specifically, it relates to a semiconductor integrated device formed at a single LSI chip, which enables testing performed by using a test pattern with an LSI tester.
FIG. 2 is a block diagram of an LSI chip in the prior art.
This LSI chip 10 is provided with an internal oscillation circuit 11 that supplies an internal clock CLK to the inside of the chip, a selector 12 that, with the clock CLK and a test clock CLKt supplied from the outside input thereto, selects either the clock CLK or the clock CLKt in based upon a select signal SL input through a select terminal Ts and a core logic unit 13 that is connected between an input terminal IN and an output terminal OUT. The core logic unit 13 takes in data provided through the input terminal IN in synchronization with the clock that has been selected by the selector 12, processes the data, and outputs the data resulting from the processing. as output data to the output terminal OUT.
An LSI tester is utilized to conduct tests using a test pattern on the LSI chip 10 described above.
The LSI tester provides the test pattern as input data to the chip 10 via the input terminal IN and also provides the selector 12 with the test clock CLKt via a clock terminal Tc. For this process, the select signal SL is set at a logic level that causes the selector 12 to select the test clock CLKt so that the test clock CLKt is provided to the core logic unit 13. The core logic unit 13 takes in and processes the test pattern provided through the input terminal IN in synchronization with the test clock CLKt, and outputs the results of the processing to the output terminal OUT.
However, the LSI chip 10 in the prior art illustrated in FIG. 2 has the following problems.
Since the operation of the core logic unit 13 during a test, which is performed in synchronization with the test clock CLKt is subject to the restrictions imposed by the maximum frequency of the test clock CLKt generated by the LSI tester, the test cannot be conducted at higher speed.
In addition, if the frequency of the internal clock CLK output by the internal oscillation circuit 11 and the frequency of the test clock CLKt are different, the evaluation cannot be made on operations performed by the core logic unit 13 on the internal clock CLK, since the LSI is not provided with any means for achieving adjustment of the difference.